In the Room
PCI Express lanes, LTSSM and the PIPE interface
How PCI Express lanes carry data, what happens during LTSSM link training, and where the PIPE interface sits between controller and physical layer.
Pieces in this section
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Who gets paid when a record plays
Composition against sound recording, performing rights organisations against SoundExchange, and the statutory licence that covers streaming but not podcasts.
14 minute read4 notes
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The wiring of a room that talks back
Console buses, the telephone hybrid, mix-minus, the profanity delay, and what happened when the wiring became a network.
13 minute read3 notes
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Loudness, and the ceiling nobody can raise
K-weighting, gating, integrated loudness, true peak, and the ten unit gap between what broadcast asks for and what streaming platforms normalise to.
14 minute read4 notes
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Microphones, and the six inches that decide everything
Dynamic against condenser, polar patterns, proximity effect, the inverse square law, and why the room usually matters more than the microphone.
12 minute read3 notes
A PCI Express link is a set of bidirectional, point-to-point serial connections called lanes, and each lane carries its own encoded bit stream in both directions at once. A link negotiated as x4 uses four lanes, an x16 slot wires sixteen, and the number of lanes is agreed during link training rather than fixed by the connector alone. The rate per lane is set by the generation in use, from 2.5 GT/s at Gen1 to 64 GT/s at Gen6, so the useful bandwidth of a link is a product of lane count, per-lane rate and the encoding overhead of that generation.
How do PCI Express lanes work?
A lane is not a bus in the shared, parallel sense. It is a pair of differential signaling pairs, one for transmit and one for receive, so a x1 link already has four wires doing work and a x16 link has sixty-four. Data is serialized onto the lane, scrambled, and encoded before it leaves the transmitter. The receiver recovers a clock from the transitions in the incoming stream, which is why the encoding scheme matters as much as the raw rate.
Each generation pairs a signaling rate with an encoding. Gen1 and Gen2 use 8b/10b, which spends two bits of overhead for every eight bits of payload, so a 5 GT/s lane delivers 4 GT/s of encoded payload before protocol overhead. Gen3 moved to 128b/130b, cutting that overhead to roughly 1.5 percent, and 16 GT/s, 32 GT/s and 64 GT/s keep the same 128b/130b framing with different modulation and forward error correction choices. The practical result is that a Gen4 x4 link and a Gen3 x8 link can land in the same bandwidth neighborhood, which is why board designers trade lanes against generation when routing space is tight.
Lanes are also independent in a way that matters for bring-up. If a x16 link trains only eight lanes because of a marginal trace or a connector fault, the link still comes up, just narrower. The operating system and the device both see the negotiated width, and the performance loss is proportional. Readers who want the per-generation tables and the encoding arithmetic laid out together can find them at PCI Express lanes, which reads the public specifications rather than vendor summaries.
What happens during LTSSM link training?
The LTSSM, the Link Training and Status State Machine, is the sequence a link walks through from power-on to a working connection. It is defined in the specification and implemented in the physical layer on both ends of the link. The states are named and ordered: Detect, Polling, Configuration, Recovery, L0, L1, L2, and the loopback and hot-reset states that sit alongside them.
Detect is the first state. Each end watches for a receiver termination on the far side, because a lane with nothing plugged in presents a different electrical signature than a lane with a live partner. Once both ends see each other, the link moves to Polling, where the two sides exchange training sequences at the lowest supported rate. Polling establishes bit lock and symbol lock, and it is the point where the receiver proves it can recover the transmitter's clock.
Configuration is where the link agrees on width and speed. The two ends exchange ordered sets that advertise how many lanes each can support, and they negotiate down to a common number. A x16 slot with a x4 card trains as x4. A x16 slot with a x16 card that has a damaged lane may train as x8 or x4. After width is settled, the link can move to a higher speed through a recovery transition, and the specification allows several speed changes before the link settles.
L0 is the normal operating state, where packets flow. L1 and L2 are low-power states entered by agreement, and the transition back to L0 is part of the same state machine. Recovery is the state used to retrain after an error or a speed change, and it can be entered from L0 without a full reset. The whole sequence is why a link that fails to train often reports a specific state in a debug register rather than a generic failure.
What is the PIPE interface in PCI Express?
PIPE, the PHY Interface for PCI Express, is the interface between the controller, usually a MAC or link layer block, and the physical layer that drives the lanes. It is not part of the PCI Express specification itself; it is a separate interface specification maintained so that controller vendors and PHY vendors can build parts that connect without a custom bus.
PIPE carries the signals that the LTSSM needs to do its work. It exposes transmit and receive data paths, the status signals that report bit lock and symbol lock, the power state controls, and the clock and reset lines. It also carries the configuration inputs that tell the PHY which generation and width to attempt. When a link trains, the controller drives the state machine and the PHY reports what it sees on the wire, and PIPE is the channel for that exchange.
PIPE has been revised alongside the generations. Early versions were parallel and wide, and later versions moved to narrower, faster interfaces to keep pin counts manageable as per-lane rates climbed. The version in use affects how a controller and PHY pair are integrated, and it is one of the details that datasheets list explicitly because a mismatch between PIPE versions can prevent a design from working even when both parts support the same PCI Express generation.
How do root complex, switches and endpoints fit together?
A PCI Express topology is a tree. At the top is the root complex, which connects the CPU and memory subsystem to the PCI Express fabric. The root complex contains one or more root ports, and each root port is the head of a link. Below the root ports sit switches, which fan out a single upstream link into several downstream links, and at the leaves sit endpoints, the devices that actually do work.
Enumeration walks this tree at boot. The configuration space of each function is read, bus numbers are assigned, and the operating system builds a picture of what is present. A switch is transparent to that process in the sense that it forwards configuration requests, but it has its own presence in the tree and its own set of ports. Endpoints appear as functions with a vendor and device identifier, and the class code tells the software what kind of device it is.
The topology matters for bandwidth because every hop adds latency and because a switch's upstream link is shared by everything below it. A x16 root port feeding a switch with four x4 downstream ports can only deliver x16 of aggregate bandwidth to those four devices combined. That arithmetic, not the lane count of any single slot, is what determines whether a storage array or a capture card will see the throughput its datasheet promises.
Why the generation and encoding numbers matter
The headline rate of a generation is a signaling rate, not a data rate. Gen1 at 2.5 GT/s with 8b/10b delivers 2 Gbit/s per lane of encoded payload, and protocol overhead takes more before application data appears. Gen3 at 8 GT/s with 128b/130b delivers close to 8 Gbit/s per lane of encoded payload, and the later generations scale from there. Comparing a x4 Gen4 link to a x8 Gen3 link on headline rate alone gives the wrong answer, because the encoding and the lane count both enter the calculation.
This is also why link training results are worth reading rather than assuming. A link that trains at a lower generation or a narrower width than expected will still function, and the only sign may be a throughput number that does not match the slot's label. The LTSSM states and the PIPE status signals are the places where that information is recorded, and the public specifications are where the state names and the encoding tables are defined.
The same layered logic that governs a PCI Express link, where lanes, LTSSM states and the PIPE interface divide labor between controller and physical layer, recurs wherever a signal path must be steered rather than merely carried. A reader who wants the radio-frequency analogue can turn to solid-state PIN switch topologies, which examines reflective and absorptive designs, what isolation and insertion loss mean in practice, and how driver timing shapes a microwave control chain. The two subjects share a concern with timing budgets and with the components that sit beside the switch in the same signal path.